A) Field of the Invention
The present invention relates to a method of forming a field oxide film (isolation film) suitable for the manufacture of a metal oxide semiconductor (MOS) type integrated circuit (IC), and more particularly to techniques of forming a channel stopper region just under the field oxide film and spaced apart from a device opening.
B) Description of the Related Art
A method of utilizing side spacers as illustrated in FIGS. 7A to 7C is known as a conventional method of forming a field oxide film with a channel stopper region just under the filed oxide film and spaced apart from the device opening (for example, refer to JP-A-HEI-5-136123).
In a process shown in FIG. 7A, after the surface of a p-type silicon substrate 1 is thermally oxidized to form a silicon oxide film 2, a silicon nitride film 3 is formed on the silicon oxide film 2 by chemical vapor deposition (CVD), and a silicon oxide film 4 is formed on the silicon nitride film 3 by CVD. A lamination of the silicon nitride film 3 and silicon oxide film 4 is patterned into a desired device opening pattern by dry etching using a resist layer as a mask.
Next, a silicon oxide film is formed on the silicon oxide film 2 by CVD, covering the lamination of the remaining silicon nitride film 3 and silicon oxide film 4, and thereafter this silicon oxide film is etched back by anisotropical etching to form a side spacer 4a on the silicon oxide film, the side spacer being made of a remaining portion of the silicon oxide film and covering the side wall of the lamination of the silicon nitride film 3 and silicon oxide film 4 in a closed loop shape. By using as a mask a lamination M of the silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4 and a lamination of the silicon oxide film 2 and side spacer 4a, boron ions B+ are implanted into a surface layer of the substrate 1 to form a channel stopper ion doped region 5a in a peripheral area of the side spacer 4a. The silicon oxide film 4, side spacer 4a and a region of the silicon oxide film 2 not covered with the silicon nitride film 2 (a region indicated by broken lines) are etched and removed by hydrofluoric acid containing chemicals. The surface of the substrate 1 not covered with the lamination of the remaining silicon oxide film 2 and silicon nitride film 3 is therefore exposed and the surface of the ion doped region 5a is also exposed.
In a process shown in FIG. 7B, a field oxide film 6 having a device opening 6A on the surface of the substrate 1 is formed by selective oxidation using as a mask the lamination of the silicon oxide film 2 and silicon nitride film 3. Heat treatment in this process forms a p-type channel stopper region 5 in conformity with the ion doped region 5a. The channel stopper region 5 is positioned just under the field oxide film 6 and spaced apart from the device opening 6A.
In a process shown in FIG. 7C, the silicon nitride film 3 and silicon oxide film 2 are sequentially etched and removed to expose the surface portion of the substrate 1 in the device opening 6A. The silicon surface in the device opening 6A is thermally oxidized to form a gate insulating film 7 made of a silicon oxide film, thereafter a gate electrode layer 8 made of doped polysilicon or the like is formed on the gate oxide film 7, and by using as a mask the filed insulating film 6 and gate electrode layer 8, impurity ions are implanted to form n+-type source/drain regions 9S and 9D. A MOS type transistor is therefore formed in the device opening 6A.
According to the above-described field oxide film forming method, the channel stopper region 5 is formed just under the field insulating film 6 and spaced apart from the device opening 6A. Therefore, as the MOS type transistor is formed in the device opening 6A as shown in FIG. 7C, (a) a pn junction will not be formed between the source/drain regions 9S and 9D and the channel stopper region 5, so that a pn junction breakdown voltage can be improved and a junction capacitance can be reduced, and (b) a channel width along a direction perpendicular to a channel longitudinal direction (a direction along which current flows between the source/drain regions) will not be narrowed by the channel stopper region 5, so that it is advantageous in that it is possible to avoid a variation (a so-called narrow channel effect) in the transistor characteristics to be caused by a narrowed channel width.
However, according to the above-described field oxide film forming method, as the silicon oxide film 4, side spacer 4a and the portion of the silicon oxide film 2 indicated by the broken line are etched and removed by hydrofluoric acid containing chemicals in the process shown in FIG. 7A, undercuts are formed in the silicon oxide film 2 just under the silicon nitride film 3. To avoid this, a field oxide film forming method has been proposed such as shown in FIGS. 8A and 8B (for example, refer to JP-A-HEI-5-136123).
In a process shown in FIG. 8A, similar to the above-description made with reference to FIG. 7A, after a silicon oxide film 2 and a silicon nitride film 3 are sequentially formed on the surface of a p-type silicon substrate 1, the silicon nitride film 3 is patterned into a desired device opening pattern. A silicon oxide film 4A is formed by CVD on the silicon oxide film 2, covering the remaining silicon nitride film 3. The silicon oxide film 4A is formed to have a closed loop portion 4b covering the side wall of the silicon nitride film 3 on the silicon oxide film 2. Thereafter, by using as a mask a lamination M′ of the silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4A and a lamination of the silicon oxide film 2 and closed loop portion of the silicon oxide film 4A, boron ions B+ are implanted into a surface layer of the substrate 1 via the lamination of the silicon oxide films 2 and 4A to form a channel stopper ion doped region 5a in a peripheral area of the closed loop portion 4b of the silicon oxide film 4A.
In a process shown in FIG. 8B, by using as a mask the lamination of the silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4A, selective oxidation is performed to form a field oxide film 6 having a device opening 5a on the surface of the substrate 1. Heat treatment in this process forms a p-type channel stopper region 5 in conformity with the ion doped region 5a. The channel stopper region 5 is positioned just under the field oxide film 6 and spaced apart from the device opening 6A. Thereafter, the silicon oxide film 4A, silicon nitride film 3 and silicon oxide film 2 are sequentially removed to form a MOS type transistor in the device opening 6A in a manner similar to that described with reference to FIG. 7C.
According to the field oxide film forming method described above with reference to FIGS. 8A and 8B, since the silicon oxide films 2 and 4A are not removed after the ion implantation process shown in FIG. 8A, it is possible to suppress an increase and variation in a bird's beak length to be caused by undercuts of the silicon oxide film 2.
A channel stopper region forming method is known by which after a field oxide film is formed by thermal oxidation, by utilizing the oxidation mask used for thermal oxidation as an ion implantation mask, ion implantation is performed via the field oxide film to form a channel stopper ion doped region (for example, refer to JP-A-HEI-6-5588 and JP-A-HEI-6-85053). In this case, in order to suppress the formation of bird's beaks, side walls made of silicon nitride and having a thickness of about 50 nm are formed on the side wall of the oxidation mask (a so-called laterally sealed local oxidation of silicon (LOCOS) method is adopted). However, with the existence of only the side wall, it is difficult to form the channel stopper ion doped region spaced apart from the device opening of the field oxide film.
According to the channel stopper region forming method described in JP-A-HEI-6-5588, the channel stopper ion doped region can be formed spaced apart from the device opening, by forming a side wall made of polysilicon and having a thickness of about 50 nm superposed upon a side wall of silicon nitride, before the ion implantation process. According to the channel stopper region forming method described in JP-A-HEI-6-85053, the channel stopper ion doped region can be formed spaced apart from the device opening, by using as an oxidation film a lamination of a silicon oxide film, a polysilicon film and a silicon nitride film stacked in this order from the bottom and by oxidizing the sides of the polysilicon film in the oxidation film during the thermal oxidation process.
Another example of a conventional field oxide film forming method is known by which a resist layer is used as an ion implantation mask as shown in FIG. 9A to 9C (for example, refer to JP-A-2000-12789.
In a process shown in FIG. 9A, after an n-type well region la and a p-type well region 1b are formed on a principal surface of a silicon substrate, a silicon oxide film 2 is formed on the principal surface by thermal oxidation, and a silicon nitride film 3 is formed on the silicon oxide film 2 by CVD. A resist layer 4B is formed on the silicon nitride film 3 above the well region 1a by a photolithography process in accordance with a desired device opening pattern. Thereafter, by using the resist layer 4B as a mask, the silicon nitride film 3 is patterned by dry etching to leave the silicon nitride film 3 having a pattern corresponding to the resist layer 4B.
Next, in a process shown in FIG. 9B, a resist layer 4C is formed on the silicon oxide film 2 by a photolithography process, exposing the resist layer 4B and a nearby silicon oxide film portion and covering the p-type well region 1b. By using the resist layers 4B and 4C as a mask, n-type impurity ions are implanted into the well region 1a to form a channel stopper ion doped region 5b. The resist layers 4B and 4C are thereafter removed.
In a process shown in FIG. 9C, by using as a mask a lamination of the silicon oxide film 2 and silicon nitride film 3, selective oxidation is performed to form a field oxide film 6 on the upper surface of the substrate 1. The field oxide film 6 is therefore formed having a device opening 6A corresponding to the silicon nitride film 3. Heat treatment in this process forms an n-type channel stopper region 5B in the surface layer of the well region 1a, in conformity with the ion doped region 5b. The channel stopper region 5B is formed having an inner end positioned in the device opening 6A. Thereafter, by applying the method previously described with reference to FIG. 7C, a MOS type transistor is formed in the device opening 6A.
According to the field oxide film forming method described with reference to FIGS. 7A to 7C, considering the process shown in FIG. 7A as a usual ion implantation process of implanting boron ions B+ at an acceleration energy of 100 keV or higher, the mask function of the lamination of the silicon oxide film 2 and side spacer 4a is not sufficient (there is a possibility of ion penetration). It is necessary to additionally form a resist layer covering the lamination M and side spacer 4a in order to reinforce the ion implantation mask. This is because an ion suppression ability of silicon oxide constituting the side spacer 4a is low. Also in the ion implantation process shown in FIG. 8A, the mask function of the lamination of the silicon oxide film 2 and closed loop portion 4b is not sufficient. It is necessary to additionally form a resist layer covering the lamination M′ and closed loop portion 4b in order to reinforce the ion implantation mask. If the resist mask is additionally formed to reinforce the ion implantation mask, a trouble may occur such as resist peel-off and lower manufacture yield.
According to the field oxide film forming method described above with reference to FIGS. 8A and 8B, a process time is elongated because of thermal oxidation via the lamination of the silicon oxide films 2 and 4A, more than the field oxide film forming method described above with reference to FIGS. 7A to 7C.
As described above, in the channel stopper region forming method by which ion implantation is performed via the field oxide film after the field oxide film is formed, and since the ion implantation is performed via the thick field oxide film of about 600 nm, it is necessary to use an expensive ion implanter having an acceleration energy of 200 keV or higher.
According to the field oxide film forming method described above with reference to FIGS. 9A to 9C, although processes are simple, since the channel stopper region 5B is formed extending in the device opening 6A, it is not possible to obtain the operation effects (a) and (b) described previously.